1. Field of the Invention
This invention relates to high performance computing network systems, and more particularly, to reducing power consumption for systems using serialized data transmission.
2. Description of the Relevant Art
The performance of computing systems is dependent on both hardware and software. In order to increase the throughput of computing systems, the parallelization of tasks is utilized as much as possible. To this end, compilers may extract parallelized tasks from program code and hardware may include multiple copies of structures to execute the parallelized tasks. The structures may include functional units, processor cores, and nodes.
Communication between the multiple structures may utilize wide communication buses. As parallelization increases, the communication buses consume more area. Additionally, cross-capacitance, electromigration interference (EMI), and parasitic inductance on wide buses increase the power consumption and noise effects of the computing system. Origins of these effects may include increased operational frequencies and reduced geometric dimensions of the wide buses themselves, bond wires, integrated circuit (IC) package leads, and external supply lines. Channel reflection or ringing, increased propagation delays, and voltage droop are some of the transmission line effects on wide buses.
Reducing the problems with high-speed parallel data transmission may include serializing the parallel data at the transmission side before transmission and then de-serializing the transmitted data on the receiver side upon reception. A pair of Serializer and Deserializer (SERDES) circuits may be used for this purpose.
The power consumption of modern integrated circuits (IC's) has become an increasing design issue with each generation of semiconductor chips. As power consumption increases, more costly cooling systems are utilized to remove excess heat and prevent IC failure. The IC power dissipation constraint is not only an issue for portable computers and mobile communication devices, but also for high-performance stationary computing systems. In order to manage power consumption, chip-level and system-level power management systems typically disable portions of the chip or system when experiencing no utilization for a given time period. This technique may reduce a number of switching nodes and load capacitance being switched.
Sleep modes and clock disabling are used to reduce the power consumption of certain portions. However, some portions may not be disabled if it is expensive to restart the structures. For example, the logic structures for the SERDES circuits typically consume an appreciable amount of time during initialization and configuration. For example, the setup may last millions of cycles. This long latency may be consumed repeatedly during system operation as the SERDES circuits are powered down and later powered back up. Accordingly, there is a significant amount of delay in data traffic, which reduces the benefit of power managing methods.
In view of the above, methods and mechanisms for reducing power consumption of systems using serialized data transmission are desired.